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rev. 1.1 1/13 copyright ? 2013 by silicon laboratories SI5355 SI5355 a ny -f requency 1?200 mh z q uad f requency 8-o utput c lock g enerator features applications description the SI5355 is a highly flexible clock generator capable of synthesizing four completely non-integer related frequencies up to 200 mhz. the device has four banks of outputs with each bank suppo rting two cmos outputs at the same frequency. using silicon laboratories' pa tented multisynth fractional divider technology, all outputs are guaranteed to have 0 ppm frequency synthesis error regardless of configuration, enabling the replacement of multiple clock ics and crystal oscillators with a single device. th rough a flexible web configuration utility called clockbuilder? ( www.silabs.com/clockbuilder ), factory-customized pin- controlled SI5355 devices are available in two weeks without minimum order quantity restrictions. the SI5355 supports up to three independent, pin-selectable device configurations, enabling one device to replace three separate clock ics. functional block diagram ? generates any frequency from 1 to 200 mhz on each of the 4 output banks ? eight cmos clock outputs ? guaranteed 0 ppm frequency synthesis error for any combination of frequencies ? 25 or 27 mhz xtal or 5?200 mhz input clk ? five programmable control pins (output enable, frequency select, reset) ? separate oeb pins to disable individual banks or all outputs ? loss of signal output ? low 50 ps (typ) pk-pk period jitter ? phase jitter: 2 ps rms 12 khz?20 mhz ? excellent psrr performance eliminates need for external power supply filtering ? low power: 45 ma (core) ? core vdd: 1.8, 2.5, or 3.3 v ? separate vddo for each bank of outputs: 1.8, 2.5, or 3.3 v ? small size: 4x4 mm 24-qfn ? industrial temperature range: ?40 to +85 c ? custom versions available using clockbuilder? web utility ? samples available in 2 weeks ? printers ? audio/video ? networking ? communications ? storage ? switches/routers ? computing ? servers ? oc-3/oc-12 line cards ordering information: see page 17. pin assignments xa clk5 clk4 vddoc vddob clk3 clk2 vdd vdd p2 clk6 clk7 los p3 vddoa clk1 clk0 gnd vddod gnd gnd xb p1 clkin p4 p5 top view 1 6 5 4 3 2 712 11 10 9 8 18 13 14 15 16 17 24 19 20 21 22 23 xa clk5 clk4 vddoc vddob clk3 clk2 vdd vdd p2 clk6 clk7 los p3 vddoa clk1 clk0 gnd vddod gnd gnd xb p1 clkin p4 p5 top view 1 6 5 4 3 2 712 11 10 9 8 18 13 14 15 16 17 24 19 20 21 22 23 free datasheet http://www.datasheet-pdf.com/
SI5355 2 rev. 1.1 free datasheet http://www.datasheet-pdf.com/
SI5355 rev. 1.1 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.1. input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2. breakthrough multisynth technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.3. input and output frequen cy configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.4. multi-function control input s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.5. output enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 3.6. frequency select/device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.7. loss-of-signal alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.8. cmos output drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.9. jitter performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.10. power supply considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.11. clockbuilder web- customization utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1. evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6. package outline: 24-lead qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7. recommended pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8. top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.1. SI5355 top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.2. top marking explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 free datasheet http://www.datasheet-pdf.com/
SI5355 4 rev. 1.1 1. electrical specifications table 1. recommended operating conditions (v dd = 1.8 v ?5% to +10%, 2.5 or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max units ambient temperature t a ?40 ? 85 o c core supply voltage v dd 2.97 3.3 3.63 v 2.25 2.5 2.75 1.71 1.8 1.98 output buffer supply voltage v ddo 1.71 ? 3.63 v note: all minimum and maximum specifications are guar anteed and apply across the recommended operating conditions. typical values apply at nominal supply vo ltages and an operating temperature of 25 c unless otherwise noted. table 2. dc characteristics (v dd = 1.8 v ?5% to +10%, 2.5 or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max units core supply current i dd 100 mhz on all outputs, 25 mhz refclk ?4560ma output buffer supply current i ddox cmos, 50 mhz 15 pf load ?69ma cmos, 200 mhz 3.3 v vdd0 ?1318ma cmos, 200 mhz 2.5 v ?1014ma cmos, 200 mhz 1.8 v ?710ma high level input voltage v ih clkin, p1 0.8 x v dd ?3.63 v p4, p5 0.85 ? 1.3 v p2, p3 1.6 ? 3.63 v low level input voltage v il clkin, p1, p2, p3 ?0.2 ? 0.2 x v dd v p4,p5 ? ? 0.3 v clock output high level output voltage v oh pins: clk0-7 i oh =?4 ma v ddo ? 0.3 ? ? v clock output low level out- put voltage v ol pins: clk0-7 i ol =+4ma ??0.3v los low level output voltage v ollos pin: los i ol =+3ma 0?0.4v pn input resistance r in ?20?k ? free datasheet http://www.datasheet-pdf.com/
SI5355 rev. 1.1 5 table 3. ac characteristics (v dd = 1.8 v ?5% to +10%, 2.5 or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max units input clock clock input frequency f in 5?200mhz clock input rise/fall time t r /t f 20?80% v dd ??2.3 ns 10?90% v dd ?? 4 ns clock input duty cycle dc input tr/tf within specified limits shown above 40 ? 60 % clock input capacitance c in ?2? pf output clocks clock output frequency f o 1?200mhz clock output frequency synthesis resolution f res see "3.3. input and output frequency configuration" on page 10 001ppb output load capacitance c l ? ? 15 pf clock output rise/fall time t r /t f 20 to 80% v dd , c l =15pf ??2.0 ns clock output rise/fall time t r /t f 20 to 80% v dd , c l =2pf ? 0.45 0.85 ns clock output duty cycle dc 45 50 55 % powerup time t pu por to output clock valid ? ? 2 ms output enable time t oeb ??10 s reset minimum pulse width t reset ??200 ns output-output skew t skew outputs at same frequency, f out > 5 mhz ?150 ? +150 ps period jitter j ppkpk 10000 cycles* ? 50 75 ps pk-pk cycle-cycle jitter* j ccpk 10000 cycles* ? 40 70 ps pk phase jitter j ph 12 khz to 20 mhz ? 2 ? ps rms pll loop bandwidth f bw ?1.6? mhz interrupt status timing clkin loss of signal assert time t los ?2.6 5 s clkin loss of signal deassert time t los_b 0.01 0.2 1 s los rise/fall time (20?80%) t r /t f c l < 10 pf, pullup < 1k ? ??10 ns *note: measured in accordance to jedec standard 65. free datasheet http://www.datasheet-pdf.com/
SI5355 6 rev. 1.1 table 4. crystal specifications parameter symbol test c ondition min typ max units crystal frequency f xtal option 1 ? 25 ? mhz option 2 ? 27 ? mhz load capacitance (on-chip differential) c l (supported)* 11 12 13 pf c l (recommended) 17 18 19 pf crystal output capacitance c o ?? 5pf equivalent series resis- tance esr 25 mhz ? ? 100 ? 27 mhz ? ? 75 ? crystal drive level rating d l 100 ? ? w *note: see "an360: crystal selection guide for si533x and SI5355/5 6 devices" for how to accommodate a 12 pf crystal c l . table 5. thermal conditions parameter symbol test condition value units thermal resistance junction to ambient ? ja still air 37 o c/w thermal resistance junction to case ? jc still air 25 o c/w table 6. absolute maximum ratings 1,2,3,4 parameter symbol rating units supply voltage range v dd ?0.5 to 3.8 v input voltage range (all pi ns except pins 1,2,5,6) v i ?0.5 to 3.8 v input voltage range (pins 1,2,5,6) v i2 ?0.5 to 1.3 v output voltage range v o ?0.5 to (v dd + 0.3) v junction temperature t j ?55 to +150 o c esd tolerance hbm 2.5 kv cdm 550 v mm 175 v latch-up tolerance lu jesd78 compliant soldering temperature (pb-free profile) 5 t peak 260 o c soldering temperature time at t peak (pb-free profile) 5 t p 20?40 sec notes: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specifie d in the operational sections of this data sheet. exposure to maximum rating conditions for extended periods may affect device reliability. 2. 24-qfn package is rohs compliant. 3. for more packaging information, go to www.silabs.com/support/qualit y/pages/rohsinformation.aspx . 4. moisture sensitivity level is msl3. 5. the device is compliant with jedec j-std-020. free datasheet http://www.datasheet-pdf.com/
SI5355 rev. 1.1 7 2. typical application circuit programmable input pins ethernet phy SI5355 4-port ethernet switch/router 33/66 mhz 125 mhz x x ethernet phy ethernet phy ethernet phy 22 18 14 10 9 25 mhz clk0 clk2 clk4 clk6 clk7 21 clk1 17 clk3 13 clk5 ethernet switch mcu/ processor 1 2 4 25 mhz xtal xa xb clkin 25 mhz 25 mhz 25 mhz 8 los 3 5 12 19 6 p1 p2 p3 p4 p5 loss of signal rse rsh rsh rse gnd gnd pad 23 23 pad +3.3v 1k 16 15 11 20 24 7 vddoa vddob vddoc vddod vdd vdd +3.3 v 0.1 uf power supply decoupling capacitors (1 per vdd or vddox pin) note: see section 3.1 for information on selecting rse and rsh. SI5355 laser printer x x 22 18 14 10 9 clk0 clk2 clk4 clk6 clk7 21 clk1 17 clk3 13 clk5 1 2 4 25 mhz xtal xa xb clkin 23 gnd gnd pad 23 pad processor 125 mhz ddr memory touchscreen controller usb controller print head paper tray lcd screen key pad 48 mhz 66/100 mhz ethernet phy 35.788 mhz x x los p1 p2 p3 p4 p5 programmable input pins 8 3 5 12 19 6 loss of signal rse rsh rsh rse +3.3v 1k 16 15 11 20 24 7 vddoa vddob vddoc vddod vdd vdd +3.3 v 0.1 uf power supply decoupling capacitors (1 per vdd or vddox pin) note: see section 3.1 for information on selecting rse and rsh. free datasheet http://www.datasheet-pdf.com/
SI5355 8 rev. 1.1 3. functional description figure 1. SI5355 functional block diagram 3.1. input configuration the SI5355 input can be driven from either an external cr ystal or a reference clock. reference selection is made when the device configuration is specified using the clockbuilder ? web-based utility available at www.silabs.com/ clockbuilder . if the crystal input option is used, the SI5355 opera tes as a free-running clock generator. in this mode of operation the device requires a low-cost 25 or 27 mhz fundamental mode crystal connected across xa and xb as shown in figure 2. given the si53 55?s frequency flexibility, the same 25 or 27 mhz crystal can be reused to generate any combination of output frequencies. cu stom frequency crystals are not required. the SI5355 integrates the crystal load capacitors on-chip to reduce external component count. the crystal should be placed very close to the device to minimize stray capacitance. to ensure stable oscillation, the re commended crystal specifications provided in table 4 on page 6 must be followed. see an360 for additional details regarding crystal recommendations. figure 2. connecting an xtal to the SI5355 for synchronous timing applications, the SI5355 can lock to a 5 to 200 mhz cmos reference clock. a typical interface circuit is shown in figure 3. a series terminatio n resistor matching the driver?s output impedance to the impedance of the transmission line is recommended to reduce reflections. figure 3. interfacing cmos reference clocks to the SI5355 xb xa xtal SI5355 clkin 50 rs SI5355 free datasheet http://www.datasheet-pdf.com/
SI5355 rev. 1.1 9 control input signals to p4 and p5 cannot exceed 1.3 v, yet also must meet the v oh and v ol specifications outlined in table 2 on page 4. when these inputs are driv en from cmos sources, a resistive attenuator as shown in the typical application circuits mu st be used. suggested standard 1% resistor values for rse and rsh are shown in table 7. 3.2. breakthrough multisynth technology next-generation timing architectures require a wide ra nge of frequencies which are often non-integer related. traditional clock architectures address this by using a co mbination of single pll ics, 4-pll ics and discrete xos, often at the expense of bom comple xity and power. the SI5355 uses pa tented multisynth technology to dramatically simplify timing architectu res by integrating the fre quency synthesis capability of 4 phase-locked loops (plls) in a single device, greatly minimizing size and powe r requirements versus traditional solutions. based on a fractional-n pll, the heart of the architecture is a lo w phase noise, high-frequency vco. the vco supplies a high frequency output clock to the multisynth block on each of the four independent output paths. each multisynth operates as a high -speed fractional divider with s ilicon laboratories' pr oprietary phase error correction to divide down the vco clock to the required output frequency with very low jitter. the first stage of the multisynth architecture is a fracti onal-n divider which switches seamlessly between the two closest integer divider values to pr oduce the exact output clock frequency with 0 ppm error. to eliminate phase error generated by this process, multisynth calculates the relative phase difference between the clock produced by the fractional-n divider and the desired output clock an d dynamically adjusts the phase to match the ideal clock waveform. this novel approach makes it possible to generat e any output clock frequency without sacrificing jitter performance. based on this architecture, the output of each multisynth can produce any frequency from 1 to 200 mhz. figure 4. silicon labs' multisynth technology table 7. 1% resistor values cmos level rse ( ? )rsh ( ? ) 1.8 v 1000 1580 2.5 v 1960 1580 3.3 v 3090 1580 fractional-n divider phase adjust phase error calculator divider select (div1, div2) f vco f out multisynth free datasheet http://www.datasheet-pdf.com/
SI5355 10 rev. 1.1 3.3. input and output frequency configuration the SI5355 utilizes a single pll-based ar chitecture, four independent multisyn th fractional output dividers, and a multisynth fractional feedback divider such that a single device provides the cl ock generation capability of 4 independent plls. unlike competitive multi-pll solution s, the SI5355 can generate four unique non-integer related output frequencies with 0 ppm frequency error for an y combination of output frequencies. in addition, any combination of output frequencies can be generated from a single reference frequency without having to change the crystal or reference clock frequency between frequency configurations. the SI5355 frequency configuration is set when the device configuration is specifie d using the clockbuilder web- based utility available at www.silabs.com/clockbuilder . any combination of output frequencies ranging from 1 to 200 mhz can be configured on each of the device outp uts. up to three unique device configurations can be specified in a single device, enabling the SI5355 to replace 3 different clock generators. 3.4. multi-function control inputs the SI5355 supports 5 user-defined input pins (pins 3, 5, 6, 12, 19) that are customizable to support the functions listed below. the pinout of each device is customized using the clockbuilder ut ility. this enables the device to be custom tailored to a specific application. each of the different functions is described in table 8. table 8. multi-function control inputs description pin function description assignable pin name oeb_all output enable all. all outputs enabled when low. p1, p2, p3, p4, or p5 oeb_a output enable bank a. clk0/1 enabled when low. p1, p2, p3, p4, or p5 oeb_b output enable bank b. clk2/3 enabled when low. p1, p2, p3, p4, or p5 oeb_c output enable bank c. clk4/5 enabled when low. p1, p2, p3, p4, or p5 oeb_d output enable bank d. clk6/7 enabled when low. p1, p2, p3, p4, or p5 fs0 frequency select. selects active device fre quency plan from factory- configured profiles. p2 fs1 frequency select. selects active device fre quency plan from factory- configured profiles. p3 reset reset. device reset required to c hange fs[1:0] pin setting. p1, p3, p4, p5 free datasheet http://www.datasheet-pdf.com/
SI5355 rev. 1.1 11 3.5. output enable each of the device?s four banks of cmos clock outp uts can be individually disabled using oeb_a, oeb_b, oeb_c, and oeb_d for clk0/1, clk2/3, clk4/5, and clk6/7, respectively. alte rnatively, all clock outputs can be disabled using the master output enabl e oeb_all. when a SI5355 clock output bank is disabled, both outputs are driven to an active low state. when one or more bank s of clock outputs are enabled or disabled, clock start and stop transitions are handled glitchlessly. 3.6. frequency select/device reset the device frequency plan is customized using the clockbu ilder web utility. the SI5355 optionally supports up to three unique, pin-selectable configurations per device, e nabling one device to replace up to three separate clock ics. to select a particular frequency plan, set the fs pins as outlined below: for custom SI5355 devices configured to support two frequency plans, the fs1 pin should be set as shown in ta b l e 9 : for custom SI5355 devices configured to support three frequency plans, the fs1 and fs0 pins should be set as shown in table 10: i f a change is made to the fs pin settings, the device re set pin (reset) must be held high for the minimum pulse width specified in table 3 on page 5 to change the devi ce configuration. the out put clocks will be momentarily squelched until the device begins operation with the new frequency plan. if the reset pin is not selected in clo ckbuilder as one of the five programmable pins, a power-on reset must be applied for an fs pin change to take effect. 3.7. loss-of-signal alarm the SI5355 includes an interrupt pin that monitors for both loss of pll lock (lol) and loss of input signal (los) conditions. the los pin is asserted whenever lol or lo s is true. the los condition occurs when there is no input clock to the device. when an input clock is remo ved, the los pin will assert, and the output may drift up to 5%. the lol condition occurs when there is a reference pr esent but it is off in frequency by a significant amount. in this condition, the los pin will asse rt and the output will be disabled. when the input clock with an appropriate frequency is reapplied, the los pin will de-assert. note that the los pin is an open-drain output. table 9. fs1 pin logic for 2 profile devices fs1 profile 01 12 table 10. fs1/fs0 pin logic for 3 profile devices fs1 fs0 profile 00reserved 011 102 113 free datasheet http://www.datasheet-pdf.com/
SI5355 12 rev. 1.1 3.8. cmos output drivers the SI5355 has 4 banks of outputs with each bank compri sed of 2 clocks for a total of 8 cmos outputs per device. each of the output banks can operate from a differen t vddo supply (1.8 v, 2.5 v, 3.3 v), simplifying usage in mixed supply applications. all clo ck outputs between 1 and 200 mhz are in-phase with minimal output-to-output skew (see table 3 on page 5 for specification). when an output bank is disabled usi ng any of the oeb functions, the clock outputs are stopped low. the cmos output driver has a controlled impedance in the range of 42 to 50 ??? which includes an internal 22 ? series resistor. an external series resistor is not needed when driving 50 ? traces. if higher impedance traces are used then a series resistor may be added. a typical configuration is shown in figure 5. figure 5. cmos output driver configuration multisynth bank a +1.8v, +2.5v, +3.3v vddoa clk0 clk1 multisynth bank c +1.8v, +2.5v, +3.3v vddoc clk4 clk5 multisynth bank d +1.8v, +2.5v, +3.3v vddod clk6 clk7 multisynth bank b +1.8v, +2.5v, +3.3v vddob clk2 clk3 pll 50 50 50 50 50 50 50 50 SI5355 free datasheet http://www.datasheet-pdf.com/
SI5355 rev. 1.1 13 3.9. jitter performance the SI5355 provides consistently low jitter for any combi nation of output frequencies. the device leverages a low phase noise single pll architecture and silicon labora tories? patented multisynth fractional output divider technology to deliver excellent jitter performance guara nteed across process, tem perature, and voltage. the SI5355 provides superior performance to conventional mu lti-pll solutions which may suffer from degraded jitter performance depending on frequency pl an and the number of active plls. 3.10. power supply considerations the SI5355 has 2 core supply voltage pins (v dd ) and 4 clock output bank supply voltage pins (v ddoa ?v ddod ), enabling the device to be used in mixed supply applicatio ns. the SI5355 does not require ferrite beads for power supply filtering. the device has ext ensive on-chip power supply regulation to minimize the impact of power supply noise on output jitter. figure 6 is a curv e of additive phase jitter with power supply noise. note that even when a significant amount of noise is app lied to the device power su pply, additive phase jit ter is still very small. figure 6. peak-to-peak additive phase jitter from 100 mv sine wave on supply 3.11. clockbuilder we b-customization utility clockbuilder is a web-ba sed utility available at www.silabs.com/clockbuilder that allows hardware designers to tailor the SI5355?s flexible clock architecture to meet an y application-specific requirements and order custom clock samples. through a simple point-and-click interface, users can specify any combination of input frequency and output frequencies and generate a custom part number for each application-specific configuration. there are no minimum order quantity restrictions. clockbuilder enables mass customization of clock generators. this allo ws a broader range of applications to take advantage of using application-specific pin controlled clocks, simplifying design wh ile eliminating the firmware development required by traditional i 2 c-programmable clock generators. based on silicon labs? patented multis ynth technology, the device pll output frequency is constant and all clock output frequencies are synthesized by the four multisynth fractional dividers. all pll parameters, including divider settings, vco frequency, loop bandwidth, charge pump curr ent, and phase margin are internally set by the device during the configuration process. this ensures optimized jitte r performance an d loop stability while simplifying design. 0 1 2 3 4 5 6 7 8 9 10 0.0001 0.001 0.01 0.1 1 modulation frequency (mhz) additive jitter (ps pk-pk) vddo vdd free datasheet http://www.datasheet-pdf.com/
SI5355 14 rev. 1.1 4. pin descriptions note: center pad must be tied to gnd for normal operation. table 11. SI5355 pin descriptions pin # pin name i/o description 1xa i external crystal. if a 25 or 27 mhz crystal is used as the dev ice frequency reference, connect it across xa and xb. if an input clock is used on pin 4, this pin should be tied to gnd. 2xb i external crystal. if a 25 or 27 mhz crystal is used as the dev ice frequency reference, connect it across xa and xb. if an input clock is used on pin 4, this pin should be tied to gnd. 3p1 i multi-function input (3.3 v tolerant). this pin functions as a multi-function input pin. the pin function (oeb_all, oeb_a, oeb_b, oeb_c, oeb_d, or reset) is user-selectable at time of configuration using the clockbuilder configuration utility. 4clkin i single-ended input clock. if a single-ended clock is used as the device frequency reference, connect it to this pin. this pin functions as a high-impedance inpu t for cmos clock signals. the input should be dc coupled. if a crystal is used as the device frequency reference, this pin should be tied to gnd. xa clk5 clk4 vddoc vddob clk3 clk2 vdd vdd p2 clk6 clk7 los p3 vddoa clk1 clk0 gnd vddod gnd gnd xb p1 clkin p4 p5 top view 1 6 5 4 3 2 712 11 10 9 8 18 13 14 15 16 17 24 19 20 21 22 23 free datasheet http://www.datasheet-pdf.com/
SI5355 rev. 1.1 15 5p4 i multi-function input. this pin functions as a multi-function input pin. the pin function (oeb_all, oeb_a, oeb_b, oeb_c, oeb_d, or rese t) is user-selectable at time of configuration using the clockbuilder configuration utility. a resi stor voltage divider is required when controlled by a signal greater than 1.3 v. see ?2. typical application circuit? for details. 6p5 i multi-function input. this pin functions as a multi-function input pin. the pin function (oeb_all, oeb_a, oeb_b, oeb_c, oeb_d, or rese t) is user-selectable at time of configuration using the clockbuilder configuration utility. a resi stor voltage divider is required when controlled by a signal greater than 1.3 v. see ?2. typical application circuit? for details. 7vddvdd core supply voltage. the device operates from a 1.8, 2.5, or 3.3 v supply. a 0.1 f bypass capacitor should be located very close to this pin. 8loso loss of signal. a typical pullup resistor of 1?4 k ? should be used on this pin. this pin functions as an input clock signal status pin. 0 = no los or lol condition 1 = los or lol condition this pin is open drain and requires an external > 1k ? pullup resistor. 9clk7o output clock 7. cmos output clock. if unused, this pin must be left floating. 10 clk6 o output clock 6. cmos output clock. if unused, this pin must be left floating. 11 vddod vdd clock output bank d supply voltage. power supply for clock outputs 6 and 7. may be operated from a 1.8, 2.5, or 3.3 v sup- ply. a 0.1 f bypass capacitor should be located very close to this pin. if clk6/7 are not used, this pin must be tied to vdd or a voltage rail of at least 1.5 v. 12 p2 i multi-function input (3.3 v tolerant). this pin functions as a multi-function input pin. the pin function (oeb_all, oeb_a, oeb_b, oeb_c, oeb_d, or fr equency select) is user-selectable at time of configura- tion using the clockbuilder configuration utility 13 clk5 o output clock 5. cmos output clock. if unused, this pin must be left floating. 14 clk4 o output clock 4. cmos output clock. if unused, this pin must be left floating. 15 vddoc vdd clock output bank c supply voltage. power supply for clock outputs 4 and 5. may be operated from a 1.8, 2.5 or 3.3 v sup- ply. a 0.1 f bypass capacitor should be located very close to this pin. if clk4/5 are not used, this pin must be tied to vdd or a voltage rail of at least 1.5 v. 16 vddob vdd clock output bank b supply voltage. power supply for clock outputs 2 and 3. may be operated from a 1.8, 2.5, or 3.3 v sup- ply. a 0.1 f bypass capacitor should be located very close to this pin. if clk2/3 are not used, this pin must be tied to vdd or a voltage rail of at least 1.5 v. table 11. SI5355 pin descriptions (continued) free datasheet http://www.datasheet-pdf.com/
SI5355 16 rev. 1.1 17 clk3 o output clock 3. cmos output clock. if unused, this pin must be left floating. 18 clk2 o output clock 2. cmos output clock. if unused, this pin must be left floating. 19 p3 i multi-function input (3.3 v tolerant). this pin functions as a multi-function input pin. the pin function (oeb_all, oeb_a, oeb_b, oeb_c, oeb_d, frequen cy select, or reset) is user-selectable at time of configuration using the clockbuilder configuration utility 20 vddoa vdd clock output bank a supply voltage. power supply for clock outputs 0 and 1. may be operated from a 1.8, 2.5, or 3.3 v sup- ply. a 0.1 f bypass capacitor should be located very close to this pin. if clk0/1 are not used, this pin must be tied to vdd or a voltage rail of at least 1.5 v. 21 clk1 o output clock 1. cmos output clock. if unused, this pin must be left floating. 22 clk0 o output clock 0. cmos output clock. if unused, this pin must be left floating. 23 gnd gnd ground. must be connected to system ground. minimize the ground path impedance for optimal performance of the device. 24 vdd vdd core supply voltage. the device operates from a 1.8, 2.5, or 3.3 v supply. a 0.1 f bypass capacitor should be located very close to this pin. gnd pad gnd gnd ground pad. this is the large pad in the center of the package. see"7. recommended pcb layout" on page 19 for the pcb pad sizes and gr ound via requirements . the device will not function unless the ground pad is properly connected to a ground plane on the pcb. table 11. SI5355 pin descriptions (continued) free datasheet http://www.datasheet-pdf.com/
SI5355 rev. 1.1 17 5. ordering guide use the clockbuil der web-based utility available at www.silabs.com/clockbuilder to specify a unique SI5355 device configuration. clockbuilder assigns a unique 5-digi t code for each unique device configuration and creates an orderable part number. the utility may also be used to or der samples, plac e production orders and look up existing part numbers. in addition, clockbuilder gener ates a data sheet addendum for each unique part number that summarizes the device input frequency, output fr equencies and other configur ation parameters for that specific part number. 5.1. evaluation board SI5355a bxxxxx g any-frequency 1?200 mhz quad frequency 8-output clock generator b = product revision b xxxxx = 5-digit custom code assigned to each unique device configuration by clockbuilder m = rohs6, pb-free qfn m r r = tape & reel blank = trays (or other) contact your silicon labs sales representative for details regarding shipment media. g = ?40 to +85 o c si5356 evb evaluation board for si5356 and SI5355 free datasheet http://www.datasheet-pdf.com/
SI5355 18 rev. 1.1 6. package outline: 24-lead qfn figure 7. 24-lead quad flat no-lead (qfn) table 12. package dimensions dimension min nom max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 b 0.18 0.25 0.30 d 4.00 bsc. d2 2.35 2.50 2.65 e 0.50 bsc. e 4.00 bsc. e2 2.35 2.50 2.65 l 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 eee 0.05 notes: 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jede c outline mo-220, variation vggd-8. 4. recommended card reflow profile is per the jedec/ip c j-std-020 specification for small body components. 5. j-std-020 msl rating: msl3. 6. terminal base alloy: cu. 7. terminal plating/grid array material: au/nipd. 8. for more packaging information, go to www.silabs.com/support/quality/ pages/rohsinformation.aspx . free datasheet http://www.datasheet-pdf.com/
SI5355 rev. 1.1 19 7. recommended pcb layout table 13. pcb land pattern dimension min nom max p1 2.50 2.55 2.60 p2 2.50 2.55 2.60 x1 0.20 0.25 0.30 y1 0.75 0.80 0.85 c1 3.90 c2 3.90 e0.50 notes: general 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994 specification. 3. this land pattern design is based on the ipc-7351 guidelines. 4. connect the center ground pad to a ground plane with no less than five vias. these 5 vias should have a length of no more than 20 mils to the ground plane. via drill size should be no smaller than 10 mils. a longer distance to the ground plane is allowed if more vias are used to keep the inductance from increasing. solder mask design 5. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 6. a stainless steel, laser-cut and electro-polished stencil wit h trapezoidal walls should be used to assure good solder paste release. 7. the stencil thickness should be 0.125 mm (5 mils). 8. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins. 9. a 2x2 array of 1.0 mm square openings on 1.25 mm pitch should be used for the center ground pad. card assembly 10. a no-clean, type-3 solder paste is recommended. 11. the recommended card reflow profile is per the jedec/ ipc j-std-020 specification for small body components. free datasheet http://www.datasheet-pdf.com/
SI5355 20 rev. 1.1 8. top marking 8.1. SI5355 top marking 8.2. top marking explanation mark method: laser line 1 marking: device part number SI5355 line 2 marking: a = frequency and co nfiguration code. pin-controlled, any-frequency 1-200 mhz, quad frequency, 8-output clock generator xxxxx = nvm code for custom factory- programmed devices. see ordering guide section in data sheet for more information. axxxxx line 3 marking: r = product revision. ttttt = manufacturing trace code. rttttt line 4 marking: pin 1 indicator. circle with 0.5 mm diameter; left-justified yy = year. ww = work week. characters correspond to the year and work week of package assembly. yyww yyww rttttt axxxxx SI5355 free datasheet http://www.datasheet-pdf.com/
SI5355 rev. 1.1 21 d ocument c hange l ist revision 0.1 to revision 0.2 ? documentation updated to reflect clkin is on pin 4, not pin 3. revision 0.2 to revision 0.3 ? added cycle-cycle and phase jitter specifications to table 3 on page 5. ? changed period jitter specification from 100 ps to 75 ps pk-pk. ? added theta jc specification to table 5 on page 6. ? updated "2. typical application circuit" on page 7. ? added table 7 on page 9. ? clarified device operation during an input clock loss of signal. ? updated recommended pcb layout. revision 0.3 to revision 1.0 ? added shipment media information for gm (vs gmr) parts. ? changed si5356 references to SI5355. ? updated vddo pin descriptions for unused clock banks. vddox associated with an unused clock bank should be tied to > 1.5 v. ? changed the name of output enable/disable control function pins in section 3.5 and tables 3, 8, and 9 to align better with the actual pin functionality. ? updated table 2. dc characteristics. ?? added iddox specification. ?? corrected pn input resi stance specification. ? updated table 3, ?ac characteristics,? on page 5. ?? added 10?90% input clock rise/fall time. ?? added los assert/deassert time. ?? added note on jitter test. ?? updated 20?80% rise/fall time with c l = 15 pf for output clocks to the ma ximum value of 2.0 ns. ?? changed frequency synthesis resolution spec to the correct value of 1ppb max. ? updated recommended crystal parameters in table 4 on page 6 to show support for both crystals rated for either 18 or 12 pf load capacitance. ? updated table 6 on page 6. ?? added soldering profile specification ?? corrected input voltage range (v i2 ) to 1.3 v (max). ?? added packaging/rohs information. ? removed jitter spec from section ?3.9. jitter performance? to prevent duplicating specs in ?table 3. ac characteristics.? ? removed output-to-output skew spec from section ?3.8. cmos output driv ers? text to prevent duplicating specs in ?table 3. ac characteristics.? ? added evaluation board information to the ordering guide. revision 1.0 to revision 1.1 ? updated ordering information to refer to revision b silicon. ? updated top marking explanation in section 8.2 free datasheet http://www.datasheet-pdf.com/
SI5355 22 rev. 1.1 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. patent notice silicon labs invests in research and development to help our cust omers differentiate in the market with innovative low-power, s mall size, analog- intensive mixed-signal solutions . silicon labs' extensive patent portfolio is a testament to our unique approach and world-clas s engineering team silicon laboratories, silicon labs, and clockbuilder are trademar ks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages. free datasheet http://www.datasheet-pdf.com/

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